Automated, Cost-Driven Decap Optimization
Sigrity X OptimizePI
Automated decoupling-capacitor selection and placement to hit PDN targets at the lowest possible cost. Save 15–50% in decap BOM cost while maintaining system performance — and run signoff up to ~8.5X faster than Sigrity 2019.
Overview
Cheapest Decap Scheme That Still Meets the Spec
OptimizePI automates the selection and placement of decoupling capacitors to meet power-delivery-network (PDN) performance targets at the lowest possible cost. It performs complete AC frequency analysis of boards and IC packages — pre-layout or post-layout — and pinpoints the best decap choices and locations.
Built on proven hybrid EM-circuit analysis combined with a unique Sigrity optimization engine — enabling true cost-based PDN design instead of trial-and-error tinkering.
15–50%
Decap BOM cost savings
while maintaining PDN performance
~8.5X
Faster than Sigrity 2019
42 hours → under 5 hours on a PCB+package run
< 30 min
Typical setup time
guided step-by-step through every task
Capabilities
What OptimizePI Does
Automated Decap Selection
The optimization engine explores the feasible design space and identifies a range of candidate decap implementations.
Optimal Placement
Find the right locations on the board / package for each decap — not just which parts to use, but where to put them.
Cost vs Performance
Interactively assess cost-vs-performance tradeoffs — pick the BOM that balances PDN signoff with bill cost.
PCB, Package, or Both
Apply to PCBs, IC packages, or a combined PCB-plus-package analysis for end-to-end PDN optimization.
Pre + Post Layout
Run early to set the right decap budget — and again post-layout to refine the implementation before tape-out.
PowerTree Integration
PowerTree information captured during schematic design feeds OptimizePI — simulate individual power rails as they develop.
Workflow
From Layout to Optimized Decap Scheme
Import Design
Bring in your PCB / package layout and PDN definition. Setup takes typically under 30 minutes.
Define Targets
Specify target impedance, rails of interest, decap part library, and any BOM / placement constraints.
Run Optimization
OptimizePI explores the design space and identifies candidate decap implementations — best parts, best locations.
Update Layout
Push the optimized decoupling scheme back into Cadence PCB design tools automatically.
Where It Fits
Part of the Sigrity X PI Signoff Stack
OptimizePI works with Clarity 3D Solver and Allegro PCB Designer for end-to-end PDN analysis — and pairs naturally with PowerSI for upstream PDN characterisation and PowerDC for DC IR-drop signoff.
Common companion tools
- PowerSI — AC frequency PI characterisation
- PowerDC — DC IR drop and thermal-aware PI
- Clarity 3D Solver — signoff EM extraction
- Allegro X PCB Designer — layout source / target
- Aurora for PCB — in-design PI checks
Get Started
Cut Decap Cost. Hit Your PDN Target. Ship Faster.
Talk to Craftronics about Sigrity X OptimizePI for automated, cost-driven decap optimization in your PCB / package flow.