Market Leader for Advanced Package Design
Allegro X Advanced Package Designer (APD)
Efficiently design, verify, and optimize complex packages with first-pass success. Cadence has led package design since the start — with a dedicated focus on building solutions for current and future packaging technology.
Key Benefits
Why Teams Choose APD
Complete Design Flow
End-to-end package design from architecture to tape-out — no toolchain gaps.
3D-IC & Heterogeneous Integration
First-class support for 3D-IC, stacked die, silicon interposers, and chiplets.
In-Design Analysis
SI / PI / thermal analysis built into the design loop — catch issues before tape-out.
Production-Proven
Tested on the world's most complex IC packaging needs — countless successful tape-outs.
Key Features
Built Specifically for Advanced Packaging
Multi-Fabric
Cross-Platform Chip / Package / Board Co-Design
Cadence is the only platform built to allow you to design and optimize the entire system — from chip, package, and board — for true multi-fabric design.
- Direct connections to Virtuoso for analog/custom IC
- Direct connection to Innovus for digital implementation
- Tight integration with Allegro X for package & PCB analysis
- Drive next-generation design closure faster and more reliably
- True system-aware design across silicon, package, and board
Purpose-Built
Designed Specifically for Advanced IC Packaging
Many IC package designers have been stuck using tools roughly shoehorned to meet their needs. APD has been built from the start with package designers in mind.
- Package-first design environment
- Native support for high-pin-count, fine-pitch parts
- All-angle and radial routing for organic substrates
- Designed for complexity, not retrofitted for it
- Countless successful tape-outs across all processes
Analysis & Verification
Next-Generation Analysis & Verification
Fully characterize designs before they are built with advanced 3D EM extraction technology — unlocking new levels of performance, capacity, and accuracy.
- Advanced 3D EM extraction for hyper-accurate models
- Industry-leading Sigrity for full SI / PI / thermal analysis
- In-design verification across chip, package, and board
- Prevent failures with up-front information
- New levels of performance, capacity, and accuracy
Any Technology. Any Process.
Comprehensive Packaging Technology Support
Design with confidence knowing APD has been proven on countless designs even at the most advanced nodes.
Lead Frame
Mechanical interfaces and advanced wirebonding.
Wirebond PBGA
2D & 3D DRC checking; all-angle / radial routing.
Flip Chip BGA
High-capacity HDI structures & routing.
Chip Scale Package (CSP)
Die stacking, HDI structures & routing.
Fan-in WLP (WLCSP)
Merged IC & package layout with GDSII output.
Fan-Out WLP (FOWLP)
Advanced outgassing with GDSII output.
Package on Package (PoP)
3D visualization & DRC, auto signal assignment.
RF Module
Virtuoso integration, parametrized structures.
More Than Moore
When the Laws of Physics Push Back
New system-in-package (SiP) technologies — silicon interposers, 3D-IC, stacked die — enable companies to achieve performance, cost, and schedule requirements without trying to rewrite the physics textbook.
SiP technologies supported
- Silicon interposers (2.5D)
- 3D-IC vertical integration
- Stacked die / multi-die packages
- Chiplet-based designs
- Heterogeneous integration
- Advanced fan-out flows
Related Products
Works Well With
Sigrity XtractIM
EM model extraction for IC packages — the natural complement to APD.
Learn More
Clarity 3D EM Solver
Full-wave EM simulation with FEM for true 3D modelling of critical interconnects.
Learn More
Celsius Thermal Solver
Comprehensive thermal & electrothermal analysis for system-level simulations.
Learn More
Allegro SystemCapture
Streamline schematic development with collaborative team design and integrated auditing.
Learn MoreFAQs
APD — Common Questions
Lead Frame, Wirebond PBGA, Flip Chip BGA, Chip Scale Package (CSP), Fan-in WLP (WLCSP), Fan-Out WLP (FOWLP), Package on Package (PoP), and RF Module — plus 3D-IC, stacked die, and silicon interposer flows.
Yes — APD has direct connections to Virtuoso (analog/custom IC) and Innovus (digital implementation), and tight integration with Allegro X for board-level analysis. This enables true chip/package/board co-design.
APD natively supports 3D-IC, heterogeneous integration, stacked die, and silicon interposers. The OrbitIO global view of system connectivity helps optimize die-bump-to-package-ball-pad assignment for the most complex multi-die designs.
Yes — Fan-in WLP (WLCSP) and Fan-Out WLP (FOWLP) designs export to GDSII for tape-out alongside silicon flows.
Sigrity XtractIM extracts EM models from APD designs. Those models feed Sigrity SI/PI/thermal flows. Clarity 3D EM Solver and Celsius Thermal Solver provide additional analysis at the package and system level.
No. APD is purpose-built for IC packaging. Allegro X PCB Editor handles board-level layout. Both run on the same platform foundation — many enterprise customers use both.
Yes — Craftronics delivers APD training including wirebond, flip-chip, WLP/FOWLP, PoP, and 3D-IC flows. In-person and virtual options available.
Yes — contact Craftronics for evaluation setup along with India-specific licensing.
Get Started
Design Your Next Advanced Package with Confidence
Talk to Craftronics about APD licensing, training, and India-specific deployment guidance.